Jiangbolong electronics officially released longsys ddr5 memory module product (Es1) today. It involves two new prototype architectures, which are 1rank X8 and 2rank X8 standard PC unbuffered DIMM 288pin on die ECC. Compared with DDR4, ddr5 has been significantly improved in function and performance.
In addition, some test data are publicly available for the first time. Among them, the test examples presented adopt Intel alderlake-s adp-s CRB development board, and use the long sys ddr5 32GB 6400 memory module, and configure the windows 10 Pro x64 operating system, and display the real data of ddr5 through two familiar software, Master Lu and aida64.
(learn from BIOS that ddr5 new architecture uses two completely independent 32-bit channels)
1. Master Lu test data
The first is the hardware configuration, and memory is identified as longsys ID.
Through Master Lu test, longsys ddr5 32GB 6400 has a running score of more than 190000.
2. Aida64 test data
Through the test, the performance score of longsys ddr5 32GB 6400 read and write copy delay can be obtained.
In order to reflect the performance improvement more intuitively, DDR4 test contrast is added. According to the data, longsys ddr5 has achieved leapfrog improvement in performance.
Core indicators disclosure
Error correction capacity increased
In optimizing the operation capability of ddr5 DRAM kernel, longsys ddr5 adds built-in error correction code (ECC), which can realize the data correction capability comprehensively, further improve the data integrity, and also alleviate the burden of error correction and make full use of the efficient mechanism of DRAM reading and writing.
Add 16N prefetch mode
BL16 makes the concurrency of longsys ddr5 memory doubled on the basis of DDR4, and the signal can be transmitted more completely and efficiently. This new ddr5 DIMM architecture uses two completely independent 32-bit channels, which improves the concurrency and doubles the available memory channels in the system.
The enhancement of end-to-end receiving mode
In addition to the dqdqsdm, the ODT function is used in the application of ddr5 new technology, and the ODT is used to add Ca and CS signals. Therefore, longsys ddr5 memory further reduces the reflection interference effect of signal pulse and makes the signal transmission more pure.
Double ddr5 Bank Group
Ddr5 memory doubles the number of banks groups and the number of banks per group remains unchanged. Longsys ddr5 BG provides less access latency, improves overall efficiency of the system and allows more pages to be opened at the same time.
Save bank refresh mode
Longsys ddr5 also implements a new feature, called “safe bank refresh” according to the standard. This command allows one bank in each BG to be refreshed so that all other banks remain open to continue normal operation.
The application scenarios in the future are constantly innovated and improved, which puts forward more stringent requirements for storage technology, and greatly accelerates the development process of ddr5. The support of major mainstream platforms for ddr5 is also promoted rapidly.
Intel expects to have ddr5 supported platforms available in the third quarter of this year, it is reported. The driving force of DRAM memory market to upgrade to ddr5 comes from professional application fields with strong demand for bandwidth, such as server, cloud computing, data center, high-performance computer and other applications, which are expected to be deployed. This iteration also provides more colorful memory solutions for industry customers.
As of March 12, 2021, the total number of longsys patents has reached 838, including 178 overseas patents; 411 authorized and maintained valid patents, 83 of which are authorized and maintained overseas; 65 software copyright.
It is reported that this year, longsys memory product line will continue to improve, and continue to provide more ddr5 product specifications and technical services.